The present invention relates in general to phase lock loops and, more particularly, to a phase lock loop with a phase lock detection feature.
Phase lock loops (PLLs) are found in a myriad of electronic applications such as modems and clock synchronization circuits for computer systems. A conventional PLL generally includes a phase detector for monitoring a phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO). The phase detector generates an up control signal and a down control signal for a charge pump to charge and discharge a loop filter at a loop node at the input of the VCO. The loop voltage developed across the loop filter determines the output frequency of the VCO. The up and down control signals driving the charge pump set the proper loop node voltage at the input of the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector.
It is common for the PLL to lose phase lock should the input signal fade or jump to a different frequency of operation. The out-of-lock state can be detected with a lock detection circuit and other system processing suspended until the PLL can re-establish phase lock. One lock detection scheme monitors the up control signal and the down control signal at the output of the phase detector to ascertain the lock status of the PLL. If the up control signal and down control signal are not pulsing, the loop node voltage remains substantially constant and the PLL should be in phase lock. When the up control signal and the down control signal are steadily generating pulses charging or discharging the loop filter to adjust the input voltage of the VCO, the loop must be in motion and thus out of phase lock.
During normal operation, the loop node is continuously subjected to leakage through the charge pump circuit thus requiring occasional pulses to maintain the voltage controlling the VCO. However, these intermittent pulses should not indicate an out-of-lock condition. The conventional lock detection circuit may include a delay circuit comprising a string of serially coupled inverters designed to ignore short intermittent pulses from the phase detector having less than a predetermined pulse width. The up and down control signals must have a pulse width at least as long as the delay circuit to trigger an out-of-lock condition. Unfortunately, the pulse widths of the up and down control signals are subject to temperature and process variation and therefore are not well suited as control parameters for ascertaining phase lock. The pulse widths of the up and down control signals are merely rough indicators having limited accuracy of the true phase relationship between the input signals of the phase detector.
Another known lock detection scheme looks at the phase difference between input signal and the output signal of the VCO as applied to the phase detector. If the transition of these signals occur outside a timeslot window, the loop is out of phase lock. The timeslot window is typically generated from the VCO frequency and requires the input signal to have a 50% duty cycle since the lock detector checks both edges of the input signal. It is desirable to eliminate the requirement for an input signal with a 50% duty cycle.
Hence, a need exists for an improved lock detection circuit for a PLL which directly monitors the input signals of the phase detector to determine the lock status of the loop, wherein the input signals may operate with a non-50% duty cycle.